The ANIC product architecture is optimized for Host Offload functions. Achieved through performing Line Rate Packet Capture and value add Packet Processing ANIC products feature Time Stamping, Packet Slicing, Packet Filtering, Buffering,  Hash Based Load Balancing and Packet Steering into Multi-Core Host CPUs.  The scalability of the ANIC architecture enables lossless packet capture and processing for the full range of packet sizes at speeds ranging from 1 GE to 40 GE.

At the heart  of  the  ANIC architecture is  a State-of-the-Art FPGA running Accolade’s Advanced Packet Processor (APP)  Firmware, Ethernet Network Interface (SFP/SPF), Packet Buffer Memory, Look Up Table (LUT) memory, Time Reference Interface and a PCIE Interface.

The APP Firmware provides a rich set of features and functionalities, accessible through a comprehensive Applications Programming Interface. Through this API, ANIC adapters can be configured for operations that offload Host CPUs in applications that include  Network Monitoring, Application Acceleration and Latency Measurement of  software tasks.

In Network Monitoring applications, ANICs support both  In-line and  Passive Packet Capture operations when connected to  the Span port of a Switch or  a Passive Network TAP.   ANICs support a variety of Host Bufferring modes which includes presenting Buffers by Port Number or presenting them in a single Buffer in Time Stamp Order of arrival.  

ANIC adapters accelerate and scale up the capacity of   Video Distribution Appliances by performing peer-to-peer Video Payload Steering while presenting  control packets to Host CPUs for execution.

Utilizing low overhead Read or Write Timer Tasks in Task Latency Measurement, applications can be configured to access the precise Reference Timer in the ANIC in three basic modes of operations. In the first 2 instances, Timer tasks can read precise time via Direct reads from the Timer Reference Register (TRR) in the APP or from a location in Host Memory where the value of the TRR or TRR Image Registeris periodically written into. The third mode of operation allows the Timer task to write into the APP’s Door Bell Fifo across the PCIE Bus. In the Door Bell Write mode of operation, Door Bell write data is time stamped, formatted into UDP packets and transmitted to an external Latency Monitoring appliance